Why Zynq?
SDSoC and HLS highlights
Zynq Architecture
Targeting Zynq with IP Integrator
Embedded System Design (Zynq) highlights
SDSoC Overview
Vivado HLS Getting started
Vivado HLS Technical Overview
Xilinx FPGA Design highlights
Vivado IP Integrator
Packaging IP
Customizing and Instantiating IP
Free training Videos
Online Resources
FPGA Resources
Zynq Resources
PYNQ Resources
Xilinx Linux Resources
Xilinx University Program Webpage
Xilinx University Program Webpage
Open Hardware is run in partnership by the Xilinx University Program, the Europractice Software Service (STFC), and CNFM
Open Hardware 2021