Development platforms
Any Xilinx device supported by Vivado can be used for the competition. AWS F1 instances and other cloud FPGA services can be used. Recommended XUP platforms include:
- TUL PYNQ-Z2
- Digilent Zybo, Zedboard, Digilent Nexys 4 DDR, Nexys 4 Video, Basys 3
- Xilinx XCU104, KCU1500, VCU1525, Alveo U200/U250
- Avnet Ultra96
Entry Submission
Xilinx Vivado or SDx software must be used to implement the design. A complete project with bitstream must be submitted. ISE entries will not be accepted.
Participants should upload complete source code and project files, a bitfile, or image, documentation, and a short project report written in English.
Participants are also required to upload a 2-minute YouTube video, and can also upload a longer video for the judge’s consideration.
Registration closes on 28th February 2019, and final project submissions must be received by midnight (anywhere in the world) on 30th June 2019
Criteria for Judging
Projects will be judged equally across all of the following categories:
- Technical Complexity (20%)
- Implementation (20%)
- Marketability/Innovation (20%)
- Documentation and Written Report (20%)
- Reusability (20%) - All participants will be encouraged to upload their projects or IP to GitHub or to demonstrate how the design or parts of the design can be reused.
For any clarification on the Rules, please contact xup@xilinx.com
XUP decision is final.
Summary of Competition Rules
Eligibility
Open Hardware is open to full-time students and PhD candidates in Europe.
Please see the rules for a list of eligible countries.
There are four categories for 2019, "PHD" (PhD candidates), "Student" for undergraduate students (Bachelors, Masters students etc), "PYNQ" and the "Compute Acceleration" category.
Individual or teams of up to three people can enter in each category.
For the student category, all participants must be undergraduate students.
If one or more participants are PhD level, the team must enter the PhD category.
For the PYNQ and Compute Acceleration categories, individuals or PhD/student teams of up to three people can enter.
All registrations must be supported by a senior member of academic staff (project Advisor) who should be from the same institute.
Applications
PhD and Student category projects can be based on any FPGA or Zynq application.
PYNQ projects can be based on any application, but must use the PYNQ Python infrastructure.
Compute acceleration projects should be based on applications that accelerate cloud FPGA or local compute intensive applications.
Target hardware is expected to be a server with host CPU connected to a PCIe FPGA acceleration board such as the Xilinx VCU1525, or the Alveo U200/U250 boards and similar.
Compute Acceleration projects can cover any application, or a library that can be used with acceleration platforms in the cloud or on local hardware. Creating new libraries, or optimization of existing open source FPGA acceleration libraries would also be a suitable application for this category.
Prizes
Two prizes will be awarded to the best projects in each of the PhD, and Student categories, and one prize will be awarded in the PYNQ and Acceleration category. i.e. 2x PhD prizes, 2x Student prizes, 1x PYNQ prize, 1x Acceleration prize. Additional prizes may be awarded at the discretion of the organiser.
Open Hardware is run in partnership by the Xilinx University Program, the Europractice Software Service (STFC), and CNFM
Open Hardware 2019
