Open Hardware



Rules





Eligibility



Open Hardware is open to students and PhD candidates in Europe. Please see the rules for a list of eligible countries.


For the 2022 edition of the competition there are four categories: "PHD" (PhD candidates), "STUDENT" for undergraduate students (Bachelors, Masters students etc), "PYNQ" and the "Compute Acceleration" category. Individual or teams of up to three people can enter in each category.

For the Student category, all participants must be undergraduate students. If one or more participants are PhD level, the team must enter the PhD category.

For the PYNQ and Compute Acceleration categories, individuals or teams of up to three people at any level up to PhD candidate can enter.

​

All registrations must be supported by a senior member of academic staff (project Advisor) who should be from the same institute.


​





Prizes



Two prizes will be awarded to the best projects in each of the PhD, and Student categories, and one prize will be awarded in the PYNQ and Compute Acceleration category, subject to the conditions outlined in the rules.

The winner in the Compute Acceleration category will also win an Alveo board (or equivalent) for their university.

Additional prizes may be awarded at the discretion of the organiser.


​





Applications



PhD and Student category projects can be based on any FPGA, ACAP or Zynq application. PYNQ projects can be based on any application, but must use the PYNQ Python infrastructure. Compute acceleration projects should be based on applications that accelerate cloud FPGA or local compute intensive applications. Target hardware is expected to be a server with host CPU connected to a PCIe FPGA acceleration hardware such as AWS-F1, Nimbix, and the Xilinx Alveo compute acceleration boards or similar. Compute Acceleration projects can cover any application, or a library that can be used with acceleration platforms in the cloud or on local hardware. Creating new libraries, or optimization of existing open source FPGA acceleration libraries would also be a suitable application for this category.







Vitis open source library



Participants interested in Compute acceleration are strongly encouraged to investigate the Open Source Vitis libraries covering BLAS, data compression, database, fintech, security, solvers, vision. Project suggestions for this category include improving an existing function or library component, adding a new function to an appropriate library, or use the open source library to build a compute acceleration application.


Vitis Open Source Library



Development platforms



Any Xilinx device supported by Vivado can be used for the competition. XACC, AWS F1 instances, and other cloud FPGA services can be used.


​





Judging criteria



Please pay careful attention to the judging criteria. Projects will be judged equally across all of the following categories:

  • Technical Complexity (20%)
  • Implementation (20%)
  • Marketability/Innovation (20%)
  • Documentation and Written Report (20%)
  • Re-usability (20%)

All participants will be encouraged to upload their projects or IP to GitHub or to demonstrate how the design or parts of the design can be reused. For any clarification on the Rules, please contact xup@xilinx.com XUP decision is final.


Xup@xilinx.com



Entry submission



Xilinx Vivado, SDx or Vitis software must be used to implement the design. A complete project with bitstream must be submitted. ISE entries will not be accepted. Participants should upload complete source code and project files, a bitfile, or image, documentation, and a short project report written in English. Participants are also required to upload a 2-minute YouTube video, and can also upload a longer video for the judge’s consideration. Registration closes on 30 February 2022, and final project submissions must be received by midnight (anywhere in the world) on 30 June 2022.